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September 2007
HYB18H512321BF-11/12/14 HYB18H512321BF-08/10
512-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM RoHS compliant
Internet Data Sheet
Rev. 1.1
Internet Data Sheet
HYB18H512321BF 512-Mbit GDDR3
HYB18H512321BF-11/12/14 HYB18H512321BF-08/10 Revision History: 2007-09, Rev. 1.1 Page 34 34 Subjects (major changes since last revision) Table 41 max. CL changed from 16 to 13 Table 41 - Timing Parameters for -8 updated
Previous Revision: Rev. 1.0, 2007-05
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22 05292007-WAU2-UU95
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HYB18H512321BF 512-Mbit GDDR3
1
1.1
* * * * * * * * * * * * * *
Overview
Features
* Data mask for write commands * Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data * Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data * DLL aligns RDQS and DQ transitions with Clock * Programmable IO interface including on chip termination (ODT) * Autoprecharge option with concurrent auto precharge support * 8k Refresh (32ms) * Autorefresh and Self Refresh * PG-TFBGA-136 package (10mm x 14mm) * Calibrated output drive. Active termination support * RoHS Compliant Product1)
This chapter lists all main features of the product family HYB18H512321BF and the ordering information.
2.0 V VDDQ IO voltage HYB18H512321BF-08/10 2.0 V VDD core voltage HYB18H512321BF-08/10 1.8 V VDDQ IO voltage HYB18H512321BF-11/12/14 1.8 V VDD core voltage HYB18H512321BF-11/12/14 Organization: 2048K x 32 x 8 banks 4096 rows and 512 columns (128 burst start locations) per bank Differential clock inputs (CLK and CLK) CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 Write latencies of 3, 4, 5, 6, 7 Burst sequence with length of 4, 8. 4n pre fetch Short RAS to CAS timing for Writes tRAS Lockout support tWR programmable for Writes with Auto-Precharge
TABLE 1
Ordering Information
Part Number1) HYB18H512321BF-11/12/14 HYB18H512321BF-08/10
1) HYB: designator for memory components 18H: VDDQ = 1.8 V 512: 512-Mbit density 32: Organization B: Product revision F: Lead- and Halogen-Free
Organisation x32
Clock (MHz) 1200/1000/900/800/700
Package PG-TFBGA-136
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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HYB18H512321BF 512-Mbit GDDR3
1.2
Description
The Qimonda 512-Mbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive applications like PC graphics systems. The chip's 8 bank architecture is optimized for high speed. HYB18H512321BF uses a double data rate interface and a 4n-pre fetch architecture. The GDDR3 interface transfers two 32 bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4n-pre fetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clockcycle data transfers at the I/O pins. Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are centeraligned with data for write commands. The HYB18H512321BF operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to both edges of RDQS. In this document references to "the positive edge of CLK" imply the crossing of the positive edge of CLK and the negative edge of CLK. Similarly, the "negative edge of CLK" refers to the crossing of the negative edge of CLK and the positive edge of CLK. References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar fashion. Read and write accesses to the HYB18H512321BF are burst oriented. The burst length is fixed to 4 and 8 and the two least significant bits of the burst address are "Don't Care" and internally set to LOW. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the column location for the burst access. Each of the 8 banks consists of 4096 row locations and 512 column locations. An AUTO PRECHARGE function can be combined with READ and WRITE to provide a self-timed row precharge that is initiated at the end of the burst access. The pipe lined, multibank architecture of the HYB18H512321BF allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. The "On Die Termination" interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register. The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (auto calibration) or to 35, 40 or 45 Ohms. Auto Refresh and Power Down with Self Refresh operations are supported. An industrial standard PG-TFBGA-136 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former DDR Graphics SDRAM products.
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2
Configuration
FIGURE 1
Ballout 512-Mbit GDDR3 Graphics RAM [Top View, MF = Low ]
1 2 3 4 ZQ 5 6 A B C D E F G H J K L M N P R T V 7 8 9 MF 10 11 12
V DDQ V SSQ V DDQ
V DD
DQ0 DQ2
V SS
DQ1 DQ3
V SS
DQ9 DQ11
V DD
DQ8 DQ10
V DDQ V SSQ V DDQ V SSQ V DDQ V DD V SS V REF V SS V DD V SS V DD V DDQ V SSQ V DDQ V SSQ V DDQ
V SSQ V DDQ V SSQ V DDQ
CAS BA0 CKE
V SSQ V DDQ V SSQ V DDQ
CS BA1 WE
V SSQ WDQS0 RDQS0 V DDQ V DD V SS V REF V SS V DD V SS V DD V DDQ
DQ4 DQ6 DM0 DQ5 DQ7 RAS RFU A2 DQ25 DQ27 DM3
RDQS1 WDQS1 DM1 DQ13 DQ15 BA2 CK A6 DQ17 DQ19 DM2 DQ12 DQ14
V SSQ
A1 RFU A10
V SSQ
A5 CK A8/AP
V DDQ
A0 A11 A3
V DDQ
A4 A7 A9
V SSQ
DQ24 DQ26
V SSQ
DQ16 DQ18
V DDQ V SSQ V DDQ V SSQ
SEN
V DDQ V SSQ V DDQ V SSQ
RESET
V SSQ WDQS3 RDQS3 V DDQ V SSQ V DDQ
DQ28 DQ30 DQ29 DQ31
RDQS2 WDQS2 DQ21 DQ23 DQ20 DQ22
V DD
V SS
V SS
V DD
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2.1
Ball Definition and Description
TABLE 2
Ball Description
Ball CLK, CLK Type Input Detailed Function Clock: CLK and CLK are differential clock inputs. Address and command inputs are latched on the positive edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are referenced to CLK. CLK and CLK are not internally terminated. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock and input buffers. Taking CKE LOW provides Power Down. If all banks are precharged, this mode is called Precharge Power Down and Self Refresh mode is entered if a Auto Refresh command is issued. If at least one bank is open, Active Power Down mode is entered and no Self Refresh is allowed. All input receivers except CLK, CLK and CKE are disabled during Power Down. In Self Refresh mode the clock receivers are disabled too. Self Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power Down without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK. The value of CKE is latched asynchronously by Reset during Power On to determine the value of the termination resistor of the address and command inputs. CKE is not allowed to go LOW during a RD, a WR or a snoop burst. Chip Select: CS enables the command decoder when low and disables it when high. When the command decoder is disabled, new commands with the exception of DTERDIS are ignored, but internal operations continue. CS is one of the four command balls. Command Inputs: Sampled at the positive edge of CLK, CAS, RAS, and WE define (together with CS) the command to be executed. Data Input/Output: The DQ signals form the 32 bit data bus. During READs the balls are outputs and during WRITEs they are inputs. Data is transferred at both edges of RDQS. Input Data Mask: The DM signals are input mask signals for WRITE data. Data is masked when DM is sampled HIGH with the WRITE data. DM is sampled on both edges of WDQS. DM0 is for DQ<0:7>, DM1 is for DQ<8:15>, DM2 is for DQ<16:23> and DM3 is for DQ<24:31>. Although DM balls are input-only, their loading is designed to match the DQ and WDQS balls. Read Data Strobes: RDQSx are unidirectional strobe signals. During READs the RDQSx are transmitted by the Graphics SDRAM and edge-aligned with data. RDQS have preamble and postamble requirements. RDQS0 is for DQ<0:7>, RDQS1 for DQ<8:15>, RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>. Write Data Strobes: WDQSx are unidirectional strobe signals. During WRITEs the WDQSx are generated by the controller and center aligned with data. WDQS have preamble and postamble requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for DQ<16:23> and WDQS3 for DQ<24:31>. Bank Address Inputs: BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED MODE REGISTER SET commands.
CKE
Input
CS
Input
RAS, CAS, WE DQ<0:31>
Input
I/O
DM<0:3>
Input
RDQS<0:3>
Output
WDQS<0:3>
Input
BA<0:2>
Input
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Ball A<0:11>
Type Input
Detailed Function Address Inputs: During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is precharged (selected by BA<0:2>, A8 LOW) or all 8 banks are precharged (A8 HIGH). During (EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are sampled with the positive edge of CLK. ODT Impedance Reference: The ZQ ball is used to control the ODT impedance. Reset pin: The RES pin is a VDDQ CMOS input. RES is not internally terminated. When RES is at LOW state the chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High transition of the RES signal is used to latch the CKE value to set the value of the termination resistors of the address and command inputs. After exiting the full reset a complete initialization is required since the full reset sets the internal settings to default. Mirror function pin: The MF pin is a VDDQ CMOS input. This pin must be hardwired on board either to a power or to a ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow for an easier routing on board for a back to back memory arrangement. Enables Boundary Scan Functionality: If Boundary Scan is not used PIN should be constantly connected to GND. Voltage Reference: VREF is the reference voltage input. Power Supply: Power and Ground for the internal logic. I/O Power Supply: Isolated Power and Ground for the output buffers to provide improved noise immunity. Please do not connect No Connect and Reserved for Future Use balls.
ZQ RESET
Input
MF
Input
SEN
Input Supply Supply Supply -
VREF VDD, VSS VDDQ, VSSQ
NC, RFU
2.2
Mirror Function
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF. This function allows for efficient routing in a clam shell configuration. Depending of the logic state applied on MF, the command and address signals will be assigned to different balls. The default ball configuration corresponds to MF = LOW. The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that. Table 3 shows the ball assignment as a function of the logic state applied on MF.
TABLE 3
Ball Assignment with Mirror
MF Logic State LOW H3 F4 HIGH H10 F9 RAS CAS Signal
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HYB18H512321BF 512-Mbit GDDR3
MF Logic State LOW H9 F9 H4 K4 H2 K3 M4 K9 H11 K10 L9 K11 M9 K2 L4 G4 G9 H10 HIGH H4 F4 H9 K9 H11 K10 M9 K4 H2 K3 L4 K2 M4 K11 L9 G9 G4 H3
Signal
WE CS CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 BA2
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2.3
Truth Tables
2.3.1
Function Truth Table for more than one Activated Bank
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the chip's multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank tRRD, tRTW and tWTR have to be taken always into account.
TABLE 4
Function Truth Table I
Current State ACTIVE Ongoing action on bank n ACTIVATE1) WRITE READ
3)
Possible action in parallel on bank m ACT, PRE, WRITE, WRITE/A, READ, READ/A2) ACT, PRE, WRITE, WRITE/A, READ, READ/A4) ACT, PRE, WRITE, WRITE/A, READ6) ACT, PRE, WRITE, WRITE/A, READ, READ/A8) ACT, PRE, WRITE, WRITE/A, READ, READ/A 8) ACT, PRE, WRITE, WRITE/A, READ, READ/A11)
WRITE/A5)
7)
READ/A9) PRECHARGE10) PRECHARGE ALL IDLE ACTIVATE 1) POWER DOWN ENTRY 12) AUTO REFRESH13) SELF REFRESH ENTRY 12) MODE REGISTER SET (MRS) EXTENDED MRS POWER DOWN SELF REFRESH
14) 14) 10) 12)
ACT 16)
POWER DOWN ENTRY
POWER DOWN EXIT15) SELF REFRESH EXIT
1) Action ACTIVATE starts with issuing the command and ends after tRCD. 2) During action ACTIVATE an ACT command on another bank is allowed considering tRRD, a PRE command on another bank is allowed any time. WR, WR/A, RD and RD/A are always allowed. 3) Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge. 4) During action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before tWTR is met. 5) Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge. 6) During action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank has to be separated by at least one NOP from the ongoing command. RD is not allowed before or tWTR is met. RD/A is not allowed during an ongoing WRITE/A action. 7) Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS. 8) During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to meet tRTW. 9) Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS. 10) Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after tRP.
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11) During Action ACTIVE an ACT command on another banks is allowed considering tRRD . A PRE command on another bank is allowed any time. WR, WR/A, RD and RD/A are always allowed. 12) During POWER DOWN and SELF REFRESH only the EXIT commands are allowed. 13) AUTO REFRESH starts with issuing the command and ends after tRFC. 14) Actions MODE REGISTER SET and EXTENDED MODE REGISTER SET start with issuing the command and ends after tMRD. 15) Action POWER DOWN EXIT starts with issuing the command and ends after tXPN. 16) Action SELF REFRESH EXIT starts with issuing the command and ends after tXSC.
2.4
Function Truth Table for CKE
TABLE 5
Function Truth Table II (CKE Table)
CKE N-1 L L H CKE n L H L CURRENT STATE Power Down Self Refresh Power Down Self Refresh All Banks Idle Bank(s) Active All Banks Idle Notes 1. 2. 3. 4. 5. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the GDDR3 Graphics RAM immediately prior to clock edge n. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND. All states and sequences not shown are illegal or reserved. DESEL or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 1000 clock cycles is required before applying any other valid command. COMMAND X X DESEL or NOP DESEL or NOP DESEL or NOP DESEL or NOP Auto Refresh ACTION Stay in Power Down Stay in Self Refresh Exit Power Down Exit Self Refresh 5 Entry Precharge Power Down Entry Active Power Down Entry Self Refresh
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3
3.1
Boundary Scan
General Description
The 512Mbit GDDR3 incorporates a modified boundary scan test mode. This mode doesn't operate in accordance with IEEE Standard 1149.1-1990. To save the current GDDR3 ball-out, this mode will scan the parallel data input and output the scanned data through the WDQS0 pin controlled by SEN.
3.2
Disabling the scan feature
It is possible to operate the 512Mbit GDDR3 without using the boundary scan feature. SEN (at U-4 of 136- ball package) should be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF, WDQS0 and CS will be operating at normal GDDR3 functionalities when SEN is deasserted.
TABLE 6
Boundary Scan Exit Order
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 Notes 1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. Two RFU balls (#56 and #57) in the scan order, will read as a logic 0. BALL D-3 C-2 C-3 B-2 B-3 A-4 B-10 B-11 C-10 C-11 D-10 D-11 BIT# 13 14 15 16 17 18 19 20 21 22 23 24 BALL E-10 F-10 E-11 G-10 F-11 G-9 H-9 H-10 H-11 J-11 J-10 L-9 BIT# 25 26 27 28 29 30 31 32 33 34 35 36 BALL K-11 K-10 K-9 M-9 M-11 L-10 N-11 M-10 N-10 P-11 P-10 R-11 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 BALL R-10 T-11 T-10 T-3 T-2 R-3 R-2 P-3 P-2 N-3 M-3 N-2 BIT# 49 50 51 52 53 54 55 56 57 58 59 60 BALL L-3 M-2 M-4 K-4 K-3 K-2 L-4 J-3 J-2 H-2 H-3 H-4 BIT# 61 62 63 64 65 66 67 BALL G-4 F-4 F-2 G-3 E-2 F-3 E-3
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TABLE 7
Scan Pin Description
PACKAGE SYMBOL BALL V-9 F-9 D-2 V-4 A-9 SSH SCK SOUT SEN SOE NORMAL FUNCTION RES CS WDQS0 SEN MF TYPE Input Input DESCRIPTION Scan Shift: Capture the data input from the pad at logic LOW and shift the data on the chain at logic HIGH. Scan Clock: Not a true clock, could be a single pulse or series of pulses. All scan inputs will be referenced to rising edge of the scan clock Scan Enable: Logic HIGH enables the device into scan mode and will be disabled at logic LOW. Must be tied to GND when not in use. Scan Output Enable: Enables (registered LOW) and disables (registered HIGH) SOUT data. This pin will be tied to VDD or GND through a resistor (typically 1K for normal operation. Tester needs to overdrive this pin to guarantee the required input logic level in scan mode.
Output Scan Output Input Input
Notes 1. When SEN is asserted, no commands are to be executed by the GDDR3. This applies both to user commands and manufacturing commands which may exist while RES is deasserted. 2. The Scan Function can be used right after bringing up VDD / VDDQ of the device. No initialization sequence of the device is required. After leaving the Scan Function it is required to run through the complete initialization sequence. 3. In Scan Mode all terminations for CMD/ADD and DQ, DM, RDQS and WDQS are switched off. 4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE's should be provided to top and bottom devices to access the scanned output. When either of the devices is in scan mode, SOE for the other device which is not in a scan will be disabled.
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4
4.1
Functional Description
Mode Register Set Command (MRS)
The Mode Register stores the data for controlling the operation modes of the memory. It programs CAS latency, test mode, DLL Reset , the value of the Write Latency and the Burst length. The Mode Register must be written after power up to operate the SGRAM. During a ModeRegister Set command the address inputs are sampled and stored in the Mode Register. The Mode Register content can only be set or changed when the chip is in Idle state. For non-READ commands following a Mode Register Set a delay of tMRD must be met. The Mode Register Bitmap is supported in two configurations. The first configuration is intended to support the Mid-RangeSpeed application. The second configuration supports higher clock cycles for CAS latency and is therefore prepared to support high-speed application. The selected configuration is defined by Bit0 of EMRS2.
FIGURE 2
Mode Register Set Command
CLK# CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
COD
BA0
0
COD: Code to be loaded into the register
BA1, BA2
0
Don't Care
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FIGURE 3
Mode Register Bitmap for Mid-Range-Speed Application
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FIGURE 4
Mode Register Bitmap for High-Speed Application
FIGURE 5
Mode Register Set Timing
CLK# CLK
Com.
PA
NOP
MRS
NOP
NOP
A.C.
NOP
RD
t RP
t MRD tMRDR
MRS: MRS command PA: PREALL command A.C.: Any other command as READ RD: READ command Don't Care
4.1.1
Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length of 4 and 8. This value must be programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block if a boundary is reached. The starting location within this block is determined by the
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two least significant bits A0 and A1 which are set internally to the fixed value of zero each.Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
4.1.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3). This device does not support the burst interleave mode.
TABLE 8
Burst Definition
Burst Length Starting Column Address A2 A1 A0 4 8 -- 0 1 X X X X X X 0-1-2-3 0-1-2-3-4-5-6-7 4-5-6-7-0-1-2-3 Order of Accesses within a Burst (Type = sequential)
The value applied at the balls A0 and A1 for the column address is "Don't care".
4.1.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. The two Mode Register setups support different CAS Latencies in terms of clock cycles. The mid-range-speed Mode Register supports latencies from 7 to 14. The high-speed Mode Register supports latencies from 10 to 17. The active Mode Register setup is selected by Bit0 of EMRS2.
4.1.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data.
TABLE 9
ON/OFF mode of DQ/DM receivers
WL 3-4 5-6-7 DQ/DM-Receivers Receivers are always on Receivers are off and will be switched on by Write command and will be switched off again after WL+BL
The ON/OFF state of the DQ/DM receivers depends on the Write Latency. The dependence is given in Table 9.
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4.1.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and A8-A11 set to the desired value.
4.1.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits A0-A7 and A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of operations once the DLL reset is completed.
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4.2
Extended Mode Register Set Command (EMRS1)
The Extended Mode Register is used to set the output driver impedance value, the termination impedance value, the Write Recovery time value for Write with Autoprecharge. It is used as well to enable/disable the DLL, to issue the Vendor ID and to enable/disable the Low Power mode. There is no default value for the Extended Mode Register. Therefore it must be written after power up to operate the GDDR3 Graphics RAM. The Extended Mode Register can be programmed by performing a normal Mode Register Set operation and setting the BA0 bit to HIGH and BA1,BA2 bits to LOW. All other bits of the EMR register are reserved and should be set to LOW. The Extended Mode Register must be loaded when all banks are idle and no burst are in progress. The controller must wait the specified time tMRD before initiating any subsequent operation (Figure 9). The timing of the EMRS command operation is equivalent to the timing of the MRS command operation.
FIGURE 6
Extended Mode Register Set Command
CLK# CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
COD
BA0
1
COD: Code to be loaded into the register
BA1, BA2
0
Don't Care
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HYB18H512321BF 512-Mbit GDDR3
FIGURE 7
Extended Mode Register Bitmap for Mid-Range-Speed Application
BA2 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
1
0
V
RFU
WR
DLL
WR
Rtt
Data Z
A6
DLL Enable Enable Disable
A1
A0
Output Driver Impedance Autocal 35 40 45
0 1
0 0 1 1
0 1 0 1
A10 0 1
Vendor ID Off
A7
A5
A4
WR
0 On 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
11 4
A3 0
A2 0 1 0 1
Termination ODT disabled RFU ZQ / 4 ZQ / 2 (Default)
2)
5 0 6 1 7 8 9 10 1
There are two bitmaps for the Extended Mode Register. One bitmap shown in Figure 7 is supposed to support Mid-Speed applications. The other bitmap shown in Figure 8 is more focused on the high-range-speed application. Both bitmaps distinguish different numbers in supported Write Recovery clock cycles. The mid-range bit map provides WR cycles from 4 to 11.The high-speed bitmap supports WR from 7 to 13.
FIGURE 8
Extended Mode Register Bitmap for High-Speed Application
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Notes 1. These settings are for debugging purposes only. 2. Default termination values at Power Up. 3. The ODT disable function disables all terminators on the device. 4. If the user activates bits in the extended mode register in an optional field, either the optional field is activated (if option implemented in the device) or no action is taken by the device (if option not implemented). 5. WR (write recovery time for auto precharge) in clock cycles is calculated by dividing tWR (in ns) and rounding up to the next integer (WR[cycles] = tWR[ns] / tCK[ns]). The mode register must be programmed to this value.
FIGURE 9
Extended Mode Register Set Timing
CLK# CLK
Command
PA
NOP t RP
EMRS
NOP t MRD
NOP
A.C.
A.C.:
Any command
EMRS: Extended MRS command PA: PREALL command
Don't Care
4.2.1
DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is enabled automatically). Anytime the DLL is enabled, 1000 cycles must occur before a READ command can be issued.
4.2.2
WR
The WR parameter is programmed using the register bits A4, A5 and A7. This integer parameter defines as a number of clock cycles the Write Recovery time in a Write with Autoprecharge operation. The following inequality has to be complied with: WR * tCKtWR, where tCK is the clock cycle time. The high-speed bitmap supports WR from 7 to 13. The mid-range bitmap provides WR cycles from 4 to 11.
4.2.3
Termination Rtt
The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports ZQ / 4 and ZQ / 2 termination values. The termination may also be disabled for testing and other purposes.
4.2.4
Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance. When the auto calibration is used, the output driver impedance is set nominally to ZQ / 6. If the Output Driver Impendance is changed to 30, 40 or 45 Ohms the user needs to issue 16 AREF commands separated by tRFC consecutively to make the change effective. The user must be aware that the Command bus needs to be stable for a time of tKO after each AREF.
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4.2.5
Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set to 1 and bits A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3 DRAM will provide the Qimonda vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will be driven onto the DQ bus after tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and Revision ID will be driven on DQ[7:0] until a new EMRS command is issued with A10 set back to 0. After tRDoff following the second EMRS command, the data bus is driven back to HIGH. This second EMRS command must be issued before initiating any subsequent operation. Violating this requirement will result in unspecified operation.
TABLE 10
Revision ID and Vendor Code
Revision Identification DQ[7:4] 0011 Qimonda Vendor Code DQ[3:0] 0010
Note: Please refer to Revision Release Note for Revision ID value.
FIGURE 10
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
0 CLK# CLK Com.
EMRS
1
2
3
4
5
6
7
8
9
10
N/D
N/D
N/D
N/D
N/D
EMRS
N/D
N/D
N/D
N/D
A[9:0], A11
Add
Add
A10 t RDQS RIDon t RIDoff
DQ[7:0]
Vendor Code and Revision ID
EMRS: Extended Mode Register Set Command Add: Address N/D: NOP or Deselect Don't Care
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HYB18H512321BF 512-Mbit GDDR3
4.3
Extended Mode Register 2 Set Command (EMRS2)
The Extended Mode Register 2 is used to define the active bitmap of the Mode Register and the Extended Mode Register. The Extended Mode Register 2 must be written after power up to operate the GDDR3 Graphics RAM. The Extended Mode Register 2 can be programmed by performing a normal Mode Register Set operation and setting the BA1 bit to HIGH and BA0, BA2 bits to LOW. All bits defined as RFU in the bitmap are reserved and must be set to LOW. The Extended Mode Register 2 must be loaded when all banks are idle and no burst are in progress. The controller must wait the specified time tMRD before initiating any subsequent operation. The timing of the EMRS2 command operation is equivalent to the timing of the MRS command operation.
FIGURE 11
Extended Mode Register 2 Set Command
CLK# CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
COD
BA1
1
COD: Code to be loaded into the register
BA0,2
0
Don't Care
FIGURE 12
Extended Mode Register 2 Bitmap
4.3.1
App Mode
The GDDR3 Graphics RAM provides two bitmaps for the Mode Register and the Extended Mode Register respectively. The Bitmaps are shown in the MRS and EMRS chapters. The Bit0 of the Extended Mode Regsiter 2 defines which one of the two bitmaps is active. Bit0 set to LOW enables the midrange bitmap and Bit0 set to HIGH enables the High-Speed bitmap.
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5
5.1
Electrical Characteristics
Absolute Maximum Ratings and Operation Conditions
TABLE 11
Absolute Maximum Ratings
Parameter Symbol Min. Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Storage Temperature Junction Temperature Short Circuit Output Current Rating Max. 2.5 2.5 2.5 2.5 +150 +125 50 V V V V C C mA Unit
VDD VDDQ VIN VOUT TSTG TJ IOUT
-0.5 -0.5 -0.5 -0.5 -55 -- --
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
5.2
DC Operation Conditions
5.2.1
Recommended Power & DC Operation Conditions
Power & DC Operation Conditions (0 C Tc 85 C)
Parameter Symbol Min. Power Supply Voltage Power Supply Voltage for I/O Buffer Limit Values Typ. 2.0 2.0 Max. 2.1 2.1 V V
1)2) 1)2)
TABLE 12
Unit Note
VDD, VDDA VDDQ
1.9 1.9
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Parameter
Symbol Min.
Limit Values Typ. 1.8 1.8 -- -- -- -- Max. 1.9 1.9 0.71*VDDQ 0.8 +5.0 +5.0 +5.0
Unit
Note
Power Supply Voltage Power Supply Voltage for I/O Buffer Reference Voltage Output Low Voltage Input leakage current CLK Input leakage current
Output leakage current -5.0 -- 1) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
VDD, VDDA VDDQ VREF VOL(DC) IIL IILC IOL
1.7 1.7 0.69*VDDQ -- -5.0 -5.0
V V V V
1)3) 1)3) 4)
5)
5)
2) HYB18H512321BF-11/12/14 3) HYB18H512321BF-08/10 4) VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% VREF (DC). Thus, from 70% of VDDQ, VREF is allowed 19mV for DC error and an additional 27mV for AC noise. 5) IIL and IOL are measured with ODT disabled.
5.3
DC & AC Logic Input Levels
DC & AC Logic Input Levels (0 C Tc 85 C)
Parameter Symbol Min. Input logic high voltage, DC Input logic low voltage, DC Input logic high voltage, AC Input logic low voltage, AC Input logic high, DC, RESET pin Input logic low, DC, RESET pin Input Logic High, DC, MF pin Input Logic Low,DC, MF pin Limit Values Max. -- V V V V V V V V
4) 1) 1) 2)3) 2)3)
TABLE 13
Unit Note
VIH(DC) VIL(DC) VIH(AC) VIL(AC) VIHR(DC) VILR(DC) VIHMF(DC) VILMF(DC)
VREF + 0.15
--
VREF -0.15
--
VREF + 0.25
-- 0.65 x VDDQ -0.3
VDD
-0.3
VREF - 0.25 VDDQ + 0.3 0.35 x VDDQ VDD + 0.3
0
1) The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. 2) Input slew rate = 3 V/ns. If the input slew rate is less than 3 V/ns, input timing may be compromised. All slew rates are measured between VIL(DC) and VIH(DC). 3) VIH overshoot: VIH(max) = VDDQ+0.5V for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. VIL undershoot: VIL(min) = 0 V for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. 4) The MF pin must be hard-wired on board to either VDD or VSS.
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5.4
Differential Clock DC and AC Levels
Differential Clock DC and AC Input conditions (0 C Tc 85 C)
Parameter Symbol Min. Clock Input Mid-Point Voltage, CLK and CLK Clock Input Voltage Level, CLK and CLK Clock DC Input Differential Voltage, CLK and CLK Limit Values Max. 0.7 x VDDQ + 0.10 V V V V
1) 1) 1)
TABLE 14
Unit Note
VMP(DC) VIN(DC) VID(DC)
0.7 x VDDQ - 0.10 0.42 0.3 0.5
VDDQ + 0.3 VDDQ VDDQ + 0.5 0.7 x VDDQ + 0.15
Clock AC Input Differential Voltage, CLK and CLK VID(AC)
1)2)
1)3) AC Differential Crossing Point Input Voltage VIX(AC) 0.7 x VDDQ - 0.15 V 1) All voltages referenced to VSS. 2) VID is the magnitude of the difference between the input level on CLK and the input level on CLK. 3) The value of VIX is expected to equal 0.7 x VDDQ of the transmitting device and must track variations in the DC level of the same.
5.5
Output Test Conditions
FIGURE 13
Output Test Circuit
VDDQ
60 Ohm
DQ DQS
Test point
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5.6
Pin Capacitances
TABLE 15
Pin Capacitances (VDDQ = 1.8 V, TA = 25C, f = 1 MHz)
Parameter Symbol Min. 1.0 2.0 Max. 2.5 3.0 Unit pF pF Note Input capacitance: CI,CCK A0-A11, , BA0-2, CKE, CS, CAS, RAS, WE, CKE, RES,CLK,CLK Input capacitance: DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0-DM3 CIO
5.7
Driver current characteristics
5.7.1
Driver IV characteristics at 40 Ohms
Figure 14 represents the driver Pull-Down and Pull-Up IV characteristics under process, voltage and temperature best and worst case conditions. The actual Driver Pull-Down and Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 , setting the nominal driver output impedance to 40 .
FIGURE 14
40 Ohm Driver Pull-Down and Pull-Up Characteristics
Table 16 lists the numerical values of the minimum and maximum allowed values of the output driver Pull-Down and Pull-Up IV characteristics.
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TABLE 16
Programmed Driver IV Characteristics at 40 Ohm
Voltage (V) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.32 4.56 6.69 8.74 10.70 12.56 14.34 16.01 17.61 19.11 20.53 21.92 23.29 24.65 26.00 27.35 28.70 30.08 -- -- Pull-Down Current (mA) Maximum 3.04 5.98 8.82 11.56 14.19 16.72 19.14 21.44 23.61 26.10 28.45 30.45 32.73 34.95 37.10 39.15 41.01 42.53 43.71 44.89 Minimum -2.44 -4.79 -7.03 -9.18 -11.23 -13.17 -15.01 -16.74 -18.37 -19.90 .21.34 -22.72 -24.07 -25.40 -26.73 -28.06 -29.37 -30.66 -- -- Pull-Up Current (mA) Maximum -3.27 -6.42 -9.45 -12.37 -15.17 -17.83 -20.37 -22.78 -25.04 -27.17 -29.17 -31.25 -33.00 -35.00 -37.00 -39.14 -41.25 -43.29 -45.23 -47.07
5.7.2
Termination IV Characteristic at 60 Ohms
Figure 15 represents the DQ termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual DQ termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 , setting the nominal DQ termination impedance to 60 . (Extended Mode Register programmed to ZQ/4).
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HYB18H512321BF 512-Mbit GDDR3
FIGURE 15
60 Ohm Active Termination Characteristic
Table 17 lists the numerical values of the minimum and maximum allowed values of the output driver termination IV characteristic.
TABLE 17
Programmed Terminator Characteristics at 60 Ohm
Voltage (V) Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -1.63 -3.19 -4.69 -6.12 -7.49 -8.78 -10.01 -11.16 -12.25 -13.27 Maximum -2.18 -4.28 -6.30 -8.25 -10.11 -11.89 -13.58 -15.19 -16.69 -18.11 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Terminator Pull-Up Current (mA) Minimum -14.23 -15.14 -16.04 -16.94 -17.82 -18.70 -19.58 -20.44 -- -- Maximum -19.45 -20.83 -22.00 -23.33 -24.67 -26.09 -27.50 -28.86 -30.15 -31.38
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HYB18H512321BF 512-Mbit GDDR3
5.8
Termination IV Characteristic at 120 Ohms
Figure 16 represents the DQ or ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 , setting the nominal termination impedance to 120 . (Extended Mode Register programmed to ZQ/2 for DQ terminations or CKE = 0 at the RES transition during Power-Up for ADD/CMD terminations).
FIGURE 16
120 Ohm Active Termination Characteristic
Table 18 lists the numerical values of the minimum and maximum allowed values of the termination IV characteristic.
TABLE 18
Programmed Terminator Characteristics of 120 Ohm
Voltage (V) Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -0.81 -1.60 -2.34 -3.06 -3.74 -4.39 -5.00 -5.58 -6.12 -6.63 Maximum -1.09 -2.14 -3.15 -4.12 -5.06 -5.94 -6.79 -7.59 -8.35 -9.06 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Terminator Pull-Up Current (mA) Minimum -7.11 -7.57 -8.02 -8.47 -8.91 -9.35 -9.79 -10.22 -- -- Maximum -9.72 -10.42 -11.00 -11.67 -12.33 -13.05 -13.75 -14.43 -15.08 -15.69
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HYB18H512321BF 512-Mbit GDDR3
5.9
Termination IV Characteristic at 240 Ohms
Figure 17 represents the ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual ADD/CMD termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 , setting the nominal termination impedance to 240 . (CKE = 1at the RES transition during Power-Up for ADD/CMD terminations).
FIGURE 17
240 Ohm Active Termination Characteristic
Table 19 lists the numerical values of the minimum and maximum allowed values of the ADD/CMD termination IV characteristic.
TABLE 19
Programmed Terminator Characteristics at 240 Ohm
Voltage (V) Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -0.41 -0.80 -1.17 -1.53 -1.87 -2.20 -2.50 -2.79 -3.06 -3.32 Maximum -0.55 -1.07 -1.58 -2.06 -2.53 -2.97 -3.40 -3.80 -4.17 -4.53 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Terminator Pull-Up Current (mA) Minimum -3.56 -3.79 -4.01 -4.23 -4.46 -4.68 -4.90 -5.11 -- -- Maximum -4.86 -5.21 -5.50 -5.83 -6.17 -6.52 -6.88 -7.21 -7.54 -7.85
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HYB18H512321BF 512-Mbit GDDR3
5.10
Operating Currents
5.10.1
Operating Current Ratings for HYB18H512321BF
Operating Current Ratings ( 0 C Tc 85 C)
Parameter Symbol Values -8 Typ Operating Current Operating Current Precharge Power-Down Standby Current Precharge Floating Standby Current Precharge Quiet Standby Current Active Power-Down Standy Current Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRC=min(tRFC)) Auto-Refresh Current at tREFI Self Refresh Current Operating Current
1) 2) 3) 4)
TABLE 20
Unit Note
-10 Typ. 580 650 380 440 450 380 540 810 800 700 475 8 860
-11 Typ. 535 600 350 410 400 350 500 740 720 660 435 8 800
-12 Typ. 500 540 315 380 350 320 460 670 660 620 400 8 740
-14 Typ. 435 415 235 310 275 235 395 575 565 535 350 8 680 mA mA mA mA mA mA mA mA mA mA mA mA mA
1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3)4) 1)2)3)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
630 705 415 470 505 410 585 885 890 740 520 8 920
IDD specifications are tested after the device is properly initialized. Input slew rate = 3 V/ns. Measured with Output open and On Die termination off. Enables on-chip refresh and address counter.
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HYB18H512321BF 512-Mbit GDDR3
5.11
Operating Current Measurement Conditions
TABLE 21
Operating Current Measurement Conditions
Symbol Parameter/Condition
IDD0
Operating Current - One bank, Activate - Precharge tCK=min(tCK), tRC=min(tRC) Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between valid commands. Operating Current - One bank, Activate - Read - Precharge One bank is accessed with tCK=min(tCK), tRC=min(tRC), CL = CL(min), Address and control inputs are SWITCHING; CS = HIGH between valid commands. Iout=0 mA Precharge Power-Down Standby Current All banks idle, power-down mode, CKE is LOW, tCK=min(tCK), Data bus inputs are STABLE (HIGH). Precharge Floating Standby Current All banks idle; CS is HIGH, CKE is HIGH, tCK=min(tCK); Address and control inputs are SWITCHING; Data bus input are STABLE (HIGH). Precharge Quiet Standby Current CS is HIGH, all banks idle, CKE is HIGH, tCK=min(tCK), Address and other control inputs STABLE (HIGH), Data bus inputs are STABLE (HIGH). Active Power-Down Standby Current One bank active, CKE is LOW, Address and control inputs are STABLE (HIGH); Data bus inputs are STABLE (HIGH); standard active power-down mode. Active Standby Current One bank active, CS is HIGH, CKE is HIGH, tRAS= tRAS,max, tCK=min(tCK); Address and control inputs are SWITCHING; Data bus inputs are SWITCHING. Operating Current - Burst Read One bank active; Continuous read bursts, CL = CL(min); tCK=min(tCK); tRAS= tRAS,max; Address and control inputs are SWITCHING; Iout = 0 mA. Operating Current - Burst Write One bank active; Continuous write bursts; tCK=min(tCK); Address and control inputs are SWITCHING; Data bus inputs are SWITCHING. Burst Auto Refresh Current Refresh command at tRFC=min(tRFC); tCK=min(tCK); CKE is HIGH, CS is HIGH between all valid commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING. Distributed Auto Refresh Current tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING. Self Refresh Current CKE max(VIL), external clock off, CK and CK LOW; Address and control inputs are STABLE (HIGH); Data Bus inputs are STABLE (HIGH). Operating Bank Interleave Read Current All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0 mA; Address and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are SWITCHING.
IDD1
IDD2P IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
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Notes 1. 0 C Tc 85 C 2. Data Bus consists of DQ, DM, WDQS. 3. Definitions for IDD: LOW is defined as VIN = 0.4 x VDDQ; HIGH is defined as VIN = VDDQ; TABLE is defined as inputs are stable at a HIGH level. SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals, and inputs changing 50% of each data transfer for DQ signals.
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5.12
AC Timings for HYB18H512321BF
TABLE 22
Timing Parameters for HYB18H512321BF
Parameter CAS latency Symbol -8 Min Clock and Clock Enable System frequency CL=13 CL= 12 CL= 11 CL =10 CL = 9 CL = 8 CL = 7 Clock high level width Clock low-level width Minimum clock half period Address/Command input setup time Address/Command input hold time Address/Command input pulse width Mode Register Set Timing Mode Register Set cycle time tMRD Mode Register Set to READ tMRDR timing Row Timing 6 12 -- -- 6 12 -- -- 6 12 -- -- 6 12 -- -- 6 12 -- -- Max 1200 1000 900 800 700 600 550 0.55 0.55 -- -- -- -- -10 Min. -- 450 400 400 400 400 400 0.45 0.45 0.45 0.24 0.24 0.7 Max. -- 1000 900 800 700 600 550 0.55 0.55 -- -- -- -- Limit Values -11 Min. -- -- 400 400 400 400 400 0.45 0.45 0.45 0.27 0.27 0.7 Max. -- -- 900 800 700 600 550 0.55 0.55 -- -- -- -- -12 Min. -- -- 400 400 400 400 400 0.45 0.45 0.45 0.3 0.3 0.7 Max. -- -- 800 700 650 550 500 0.55 0.55 -- -- -- -- -14 Min. -- -- 400 400 400 400 400 0.45 0.45 0.45 0.35 0.35 0.7 Max. -- -- 700 650 600 500 450 0.55 0.55 -- -- -- -- MHz MHz MHz MHz MHz MHz MHz
1) 1) 1) 1) 1) 1)
Unit Note
fCK13 fCK12 fCK11 fCK10 fCK9 fCK8 fCK7 tCH tCL tHP tIS tIH tIPW
700 450 400 400 400 400 400 0.45 0.45 0.45 0.22 0.22 0.7
tCK tCK tCK
ns ns
2)
Command and Address Setup and Hold Timing
tCK
tCK tCK
3)4)
tRC Row Active Time tRAS ACT(a) to ACT(b) Command tRRD
Row Cycle Time period Row Precharge Time Row to Column Delay Time for Reads Row to Column Delay Time for Writes Four Active Windows within Rank
40 25 10 15 14
-- -- -- -- --
37 23 9 14 13
-- -- -- -- --
35 22 8 13 12
-- -- -- -- --
34 21 8 13 12
-- -- -- -- --
30 18 7 12 11
-- -- -- -- --
tCK tCK tCK tCK tCK tCK
5)
tRP tRCDRD tRCDWR tFAW
tRCDWR(Min) = max(tRCDRD(Min) - (WL + 1) x tCK;2xtCK)
40 -- 36 -- 32 -- 32 -- 28 --
6)
tCK
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Parameter
CAS latency Symbol -8 Min Max -- -- -10 Min. 2 7 Max. -- --
Limit Values -11 Min. 2 6 Max. -- -- -12 Min. 2 6 Max. -- -- -14 Min. 2 5 Max. -- --
Unit Note
Column Timing CAS(a) to CAS(b) Command tCCD period Write to Read Command Delay Read to Write command delay Write command to first WDQS latching transition Data-in and Data Mask to WDQS Setup Time Data-in and Data Mask to WDQS Hold Time Data-in and DM input pulse width (each input) DQS input low pulse width DQS input high pulse width DQS Write Preamble Time DQS Write Postamble Time Write Recovery Time Data Access Time from Clock Read Preamble Read Postamble Data-out high impedance time from CLK 2 8
tCK tCK tCK
7)
tWTR tRTW
8)
tRTW(min)= (CL + BL/2 +2 -WL)
9)
Write Cycle Timing Parameters for Data and Data Strobe
tDQSS tDS tDH tDIPW tDQSL tDQSH tWPRE tWPST tWR tAC tRPRE tRPST tHZ
WL- 0.25 0.13 0.13 0.4 0.45 0.45 0.75 0.75 13
WL+ 0.25 -- -- -- -- -- 1.25 1.25 --
WL- WL+ 0.25 0.25 0.14 0.14 0.40 0.40 0.40 0.75 0.75 13 -- -- -- -- -- 1.25 1.25 --
WL- WL+ 0.25 0.25 0.15 0.15 0.40 0.40 0.40 0.75 0.75 13 -- -- -- -- -- 1.25 1.25 --
WL- WL+ 0.25 0.25 0.16 0.16 0.40 0.40 0.40 0.75 0.75 12 -- -- -- -- -- 1.25 1.25 --
WL- 0.25 0.18 0.18 0.40 0.40 0.40 0.75 0.75 10
WL+ 0.25 -- -- -- -- -- 1.25 1.25 --
tCK
ns ns
tCK tCK tCK tCK tCK tCK
ns
Read Cycle Timing Parameters for Data and Data Strobe -0.20 -0.20 -0.21 0.21 0.75 0.75 1.25 1.25 0.75 0.75 1.25 1.25 -0.22 0.22 0.75 0.75 1.25 1.25 -0.22 0.22 0.75 0.75 1.25 1.25 -0.25 0.25 0.75 0.75 1.25 1.25
tCK tCK
tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ns tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ns
-0.20 0.20 -- -- -0.21 0.21 -0.22 0.22 -0.22 0.22 -0.25 0.25 ns
10)
Data-out low impedance time tLZ from CLK DQS edge to Clock edge skew DQS edge to output data edge skew Data hold skew factor Data output hold time from DQS
tDQSCK tDQSQ tQHS tQH
0.110 -- 0.110 --
0.120 -- 0.120 --
0.130 -- 0.130 --
0.140 -- 0.140 --
0.160 ns 0.160 ns ns
tHP-tQHS
Refresh/Power Down Timing Refresh Period (8192 cycles) tREF Average periodic Auto Refresh interval -- 3.9 32 -- 3.9 32 -- 3.9 32 -- 3.9 32 -- 3.9 32 ms s
tREFI
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HYB18H512321BF 512-Mbit GDDR3
Parameter
CAS latency Symbol -8 Min Max -- -10 Min. 52.0 Max. --
Limit Values -11 Min. 52.0 Max. -- -12 Min. 52.0 Max. -- -14 Min. 52.0 Max. --
Unit Note
Delay from AREF to next ACT/ AREF Self Refresh Exit time Power Down Exit time Other Timing Parameters RES to CKE setup timing RES to CKE hold timing Termination update Keep Out timing Rev. ID EMRS to DQ on timing Rev. ID EMRS to DQ off timing
1) 2) 3) 4) 5) 6) 7) 8) 9) 10)
tRFC tXSC tXPN tATS tATH tKO tRIDon tRIDoff
52.0
ns
1000 -- 7 10 10 10 -- -- -- -- -- -- 20 20
1000 -- 7 10 10 10 -- -- -- -- -- -- 20 20
1000 -- 7 10 10 10 -- -- -- -- -- -- 20 20
1000 -- 7 10 10 10 -- -- -- -- -- -- 20 20
1000 -- 6 10 10 10 -- -- -- -- -- -- 20 20
tCK tCK
ns ns ns ns ns
DLL on mode ( -8/10/-11/-12/-14 fCK(Min) = 400 MHz) tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs This value of tMRD applies only to the case where the "DLL reset" bit is not activated tMRD is defined from MRS to any other command then READ tRASmax is 8xtREF tRCDWR(Min) may not drop below 2 x tCK tCCD is either for gapless consecutive reads or gapless consecutive writes. BL =4 WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal Please round up tRTW to the next integer of tCK This parameter is defined per byte
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Internet Data Sheet
HYB18H512321BF 512-Mbit GDDR3
6
6.1
Package
Package Outline
FIGURE 18
Package Outline PG-TFBGA-136-054
Note: The package is conforming with JEDEC MO-207i, VAR DR-z.
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Internet Data Sheet
HYB18H512321BF 512-Mbit GDDR3
6.2
Package Thermal Characteristics
TABLE 23
PG-TFBGA-136 Package Thermal Resistances
Theta_jA JEDEC Board Air Flow K/W Notes 1. Theta_jA: Junction to Ambient thermal resistance. The values have been obtained by simulation using the conditions stated in the JEDEC JESD-51 standard. 2. Theta_jB: Junction to Board thermal resistance. The value has been obtained by simulation. 3. Theta_jC: Junction to Case thermal resistance. The value has been obtained by simulation. 1s0p 0 m/s 40 1 m/s 32 3 m/s 27 2s0p 0 m/s 22 1 m/s 19 3 m/s 17 5 2 Theta_jB Theta_jC
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Internet Data Sheet
HYB18H512321BF 512-Mbit GDDR3
List of Illustrations
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Ballout 512-Mbit GDDR3 Graphics RAM [Top View, MF = Low ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mode Register Set Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Mode Register Bitmap for Mid-Range-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Mode Register Bitmap for High-Speed Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Extended Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Extended Mode Register Bitmap for Mid-Range-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Extended Mode Register Bitmap for High-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Timing of Vendor Code and Revision ID Generation on DQ[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Extended Mode Register 2 Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Extended Mode Register 2 Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 40 Ohm Driver Pull-Down and Pull-Up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 120 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outline PG-TFBGA-136-054 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ball Assignment with Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Function Truth Table I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Function Truth Table II (CKE Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Boundary Scan Exit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Scan Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ON/OFF mode of DQ/DM receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision ID and Vendor Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power & DC Operation Conditions (0 C Tc 85 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC & AC Logic Input Levels (0 C Tc 85 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Differential Clock DC and AC Input conditions (0 C Tc 85 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Capacitances (VDDQ = 1.8 V, TA = 25C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Programmed Driver IV Characteristics at 40 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Programmed Terminator Characteristics at 60 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Programmed Terminator Characteristics of 120 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Programmed Terminator Characteristics at 240 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating Current Ratings ( 0 C Tc 85 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Timing Parameters for HYB18H512321BF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PG-TFBGA-136 Package Thermal Resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Contents
1 1.1 1.2 2 2.1 2.2 2.3 2.3.1 2.4 3 3.1 3.2 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.3 4.3.1 5 5.1 5.2 5.2.1 5.3 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.8 5.9 5.10 5.10.1 5.11 5.12 6 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mirror Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Function Truth Table for more than one Activated Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Function Truth Table for CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disabling the scan feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Command (MRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Set Command (EMRS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination Rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vendor Code and Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register 2 Set Command (EMRS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . App Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings and Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Power & DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Clock DC and AC Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver IV characteristics at 40 Ohms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Ratings for HYB18H512321BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timings for HYB18H512321BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 15 16 16 16 17 17 18 20 20 20 20 21 22 22 23 23 23 23 24 25 25 26 26 26 27 29 30 31 31 32 34
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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6.2 Package Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Internet Data Sheet
Edition 2007-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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